This paper proposes a 2.4 GHz active mixer without passive inductor for the transceiver system. Taking into account the design requirements of the mixer, a double-balanced down-conversion structure with active inductor and negative resistance is designed. The proposed mixer with 130 nm CMOS technology is designed and simulated using Cadence software at 1.5 V supply voltage. Although we had to compromise conversion gain with linearity, we were able to achieve very HIGH conversion gain with average linearity. Based on the results of post-layout simulations, the conversion gain of 27.57 dB, IIP3 equal to -7.88 dBm, 1-dB compression point equal to -17.34 dBm and IIP2 equal to 44.22 dBm with POWER consumption of 2.5 mW was obtained for the proposed mixer. The chip size without input and output pads is 95.18 µm × 117.68 µm, which leads to a chip area of 0.0112mm2.

The use of smart radio equipment with HIGH performance is one of the requirements of the smart police, and in this regard, it is necessary to consider operational requirements in the design of different parts of the radio transmitter and receiver. In the transmitter section, the POWER AMPLIFIER has some features such as POWER consumption, output POWER, and POWER added efficiency which are significant items in the design. This paper deals with the design of HIGH- performance Class-E POWER AMPLIFIERs for the Radio communication systems. For this purpose, a cascade structure consisting of an AMPLIFIER is used as a switch to amplify the signal and an AMPLIFIER to increase reliability. In this circuit, one transistor is biased in the triode region as a switch and the other transistor is biased in the triode or saturation region. In this paper, a cascade class E POWER AMPLIFIER with a driver circuit and a compensator circuit is proposed to increase the output POWER and POWER added efficiency (PAE). The presented PA in this paper is appropriate for Radio communication. In this paper, the output POWER and PAE is improved by changing the structure of the PA. The PA has 2.6 GHz operating frequency, output POWER of 31.4 dBm, maximum PAE of 55.5%. The designed circuits are simulated with Cadence software.

This paper presents a new extended HIGH-efficiency range Doherty AMPLIFIER. This AMPLIFIER uses a main and only a single auxiliary AMPLIFIER. In order to increase efficiency and extend the output HIGH-efficiency range, asymmetrical cells are employed as the main and auxiliary AMPLIFIERs in class-F harmonic termination complex combining load (CCL) methodology. To verify the proposed methodology, a Doherty POWER AMPLIFIER (DPA) with 12 dB output back-off (OBO) is designed and fabricated for wideband code division multiple access (WCDMA) applications. Large signal continuous wave measurement results show the POWER gain of about 10. 9 dB with a drain efficiency of 66 % at 12 dB of OBO. A two-tone test exhibits a third-order intermodulation distortion (IMD) of lower than-21. 5 dBc. Modulated wave measurements show over 56. 5 % of average drain efficiency and an adjacent channel leakage POWER ratio (ACLR) of lower than-26. 5 dBc at an output POWER level of 31. 5 dBm.

A HIGH-gain, fully balanced preAMPLIFIER is presented. The proposed structure advantages flipped voltage follower scheme to achieve a compact current conveyor with very low input impedance. The presented current conveyor then is used as a core element to realize a HIGH-gain, gm-enhanced trans-conductance AMPLIFIER. The presented AMPLIFIER is suitable for application as a preAMPLIFIER. The HIGH gain of AMPLIFIER makes it very suitable to be configured in a feedback form to deliver a HIGH-precision predefined or programmable amplification gain. The proposed structure draws a very low POWER of 150nW from a 0.6V supply voltage. The Spectre Post-layout simulations with TSMC 180nm CMOS technology have been performed. The proposed amplifier exhibits an open-loop DC gain of 141.5dB and 3-dB frequency bandwidth of 2.4kHz at 60dB closed-loop configuration. The load capacitance is set to be 5pF. The proposed structure also delivers HIGH CMRR and PSRR values of 148.3dB and 153.7dB, respectively.

The graphical technique for nonlinear circuits was described that enable us to optimize circuits to obtain maximum output POWER, maximum efficiency or minimum intermodulation.According to this method a HIGH POWER AMPLIFIER in the Ka band was designed. Using a nonlinear model of the transistor, optimum slope for load-line was determined so that maximum POWER at the output was obtainable, then the output matching circuit was synthesized. Finally, the nonlinear network of the HIGH POWER AMPLIFIER was analyzed by the harmonic balance method and the output load cycles were optimized by modification of the bias point or output matching network.

In this paper, we have presented an X band HIGH POWER AMPLIFIER based on MMIC (Monolithic Microwave Integrated Circuit) technology for satellite remote sensing systems. We have used GaN HEMT process with 500 nm gate length technology with VD= 40 V and VG=-2 V in class E structure. The proposed two-stage POWER AMPLIFIER provides 25 dB POWER gain with maximum output POWER of 49. 3 dBm at 10 GHz. Bandwidth of proposed HIGH POWER AMPLIFIER is 2 MHz and we have achieved 49% POWER Added Efficiency (PAE). We have designed a band pass filter for decreasing of memory effects in output. The active on chip area of layout obtained 35 mm2 (8. 2 mm × 4. 3 mm). We have obtained AM/PM and AM/AM,-3. 8deg and 1 dB respectively in the worst case. The proposed POWER AMPLIFIER is unconditionally stable at the satisfied frequency range.

In this paper a Class-D AMPLIFIER is proposed to drive piezoelectric loads considering efficiency, linearity and electromagnetic interference issues. The proposed class-D AMPLIFIER is based on pulse-width-modulation (PWM) battery-fed. The AMPLIFIER not only supplies HIGH voltage POWER but also utilizes dc-to-dc chopper to make electric isolation and reduce the output distortion. Using isolation dc chopper, causes AMPLIFIER isolation from the battery and in turn leads the circuits to be secured from the output distortions. The proposed class-D AMPLIFIER consists of a close-loop H-bridge ac-to-dc converter to improve the gain and reduce the output distortion. The AMPLIFIER is linear and the achieved output voltage THD is less than 0. 9% by a band-pass filter. The proposed AMPLIFIER is analyzed in different modes precisely and its operation is simulated. Main features are electric isolation from the source, linearity, fast response and sufficient band-pass.

In this article, HIGH frequency POWER AMPLIFIER is designed based on monolithic microwave integrated circuit (MMIC) technology. For this design the process of GaN transistors with HIGH electron mobility has been used and its length gate technology is 150nm central frequency of the AMPLIFIER is 2. 5GHz. the maximum gain of the AMPLIFIER is approximately equal to 12. 76dB and is designed in one stage. At this frequency, the maximum output POWER of the AMPLIFIER is about 39. 196 dBm in 30dBm input. In the maximum output POWER, PAE is about 41. 25% that this is maximum amount of PAE. The final area of the circuit for embedding on the chip is 25. 903mm by 19. 346mm. the maximum values of AM/PM and AM/AM are 2. 38deg/db and 1. 66dB/dB respectively. For the 3-rd intermodulation distortion (IMD3) is about-20 dBc at the center of frequency. To design this AMPLIFIER, Loadpull analysis of ADS software was used to obtain the appropriate output POWER.

This paper presents the design and evaluation of a HIGH-efficiency harmonic tuned L-band POWER AMPLIFIER (PA) utilizing a Gallium Nitride (GaN) HIGH Electron Mobility Transistor (HEMT). To meet the demands of modern wireless communication and radar systems operating in the L-band, advanced harmonic tuning techniques were employed, specifically focusing on controlling the impedance terminations at the second (2f₀) and third (3f₀) harmonic frequencies. Through careful load-pull analysis and optimized output matching network design, precise harmonic terminations were achieved alongside optimal fundamental frequency impedance matching. The fabricated PA demonstrates state-of-the-art performance, delivering a saturated output POWER (Psat) of 46.4 dBm with a corresponding peak POWER Added Efficiency (PAE) of 83%. Critically, the PA maintains HIGH efficiency under back-off conditions, achieving 60% PAE at 3 dB output back-off (OBO). These results HIGHlight the effectiveness of this combined second and third harmonic optimization approach with GaN HEMT technology, which enables both HIGH peak efficiency and excellent back-off efficiency for demanding L-band applications.

This paper presents a novel hybrid Class-E/FJ POWER AMPLIFIER (PA) that integrates Class-E/F PA and Class-J PA to formulate a HIGH-efficiency as well as broadband performance. The theoretical relationships of the Class-E/F AMPLIFIER have been thoroughly examined, and the corresponding relationships and diagrams have been obtained. Furthermore, in the next step, theoretical analysis for Class-J has been derived, and the necessary conditions for achieving a strengthening relationship between Class-E/F and Class-J to achieve a hybrid Class-E/FJ PA have been investigated. Through the judicious configuration of parameter values, the proposed design achieves an efficiency range spanning from 61.2% to 73.4% across the 1.3-3.1 GHz. The paper delineates a systematic design process for a broadband Class-E/FJ PA based on derived theories. To validate the proposed approach, a meticulous design and fabrication process is undertaken for a 1.3-3.1 GHz broadband Class-E/FJ PA. Measurement results demonstrate that the PA can deliver a saturated output POWER ranging from 39.3 dBm to 42 dBm, accompanied by a gain within the 8-12 dB range. Additionally, the POWER Added Efficiency (PAE) falls within the range of 58.9%-67% within the specified frequency band. A comparative analysis with similar predecessors reveals that the proposed PA outperforms others, exhibiting superior performance across a wide bandwidth.